1. Field of the Invention
The present invention relates to integrated circuit chip testing procedures, and particularly to a circuit and method providing dynamic scan chain partitioning to reduce power during chip testing.
2. Description of the Related Art
Scan-based testing has become the standard in testing VLSI circuits due to the enhanced controllability and observability it provides. High fault coverage levels can be attained by serially inserting the test stimulus into the scan chains through the scan-in pins, by applying it to the circuit, and by serially collecting the responses through the scan-out pins. Enhanced accessability, however, is reaped at the expense of increased switching activity. During the shift cycles, any scan cell may potentially toggle. Furthermore, the transitions that stem from the toggling scan cells propagate into the combinational logic being tested, triggering more transitions there. As a result, scan-based testing suffers from elevated power dissipation.
The total switching activity generated throughout the test process constitutes the energy. Average power is the ratio of energy to the duration of the complete test process. High average power during testing leads to the overheating of the chip and, thus, endangers its reliability. Instantaneous power, on the other hand, is the value of power dissipation at a given point in time, while peak power is defined by the maximum instantaneous power. In computing the peak power, the time instants wherein toggling occurs is of particular focus; for positive-edge flip-flops, these time instants are marked by the rising edges of the clock. Excessive peak power levels, especially levels beyond which the chip can functionally operate at, may lead to an unexpected behavior of the circuit. Consequently, observed responses differ from the expected ones, resulting in a yield loss. While average power can be reduced by slowing down the shift clock, and thus suffering from prolonged test application time, even such an approach is of no remedy for peak power.
Power dissipation can be decomposed into three components. The first component is the power dissipation within the scan chains, while the second component is the power dissipation within the combinational logic as a consequence of the toggling of the scan cells. The third component is the power dissipated within the clock tree, which is due to the toggling of the clock lines that feed the scan path. Clock power dissipation has been shown to be the major contributor of test power and thus needs to be handled in addition to the power dissipation of the scan path and the combinational logic.
A solution that targets the reduction of all three contributing factors of test power is scan chain partitioning. In such a scheme, only a subset of the scan chains may be toggling at any instance, while all the remaining chains preserve their content. This can be attained by manipulating the test clock of the scan chains. The clock network, the scan path, and the combinational logic associated with the non-toggling scan chains do not dissipate any power, as they are all idle. The power reduction level is determined by the amount of switching activity that occurs in the toggling part of the design.
Peak power, by definition, is dictated by one cycle of one test pattern (excluding the possibility of transition-wise ties among different cycles) wherein the highest level of toggling occurs. Thus, peak power reduction necessitates the special handling of this problematic test pattern. Ideally, the chains should be partitioned in such a way that the transitions of this pattern are evenly distributed over multiple time instants within the shift cycle, maximally reducing the peak power. Static partitioning of the scan chains, namely, the identical partitioning of chains for all the test patterns, may fail to deliver this special handling for the problematic pattern; highly toggling chains may be grouped together within the same partition, failing to deliver a significant peak power reduction. To minimize peak power, scan chain partitioning can be customized based on a given test set. However, a single partitioning may be incapable of evenly distributing the transitions of all the problematic patterns. Furthermore, such a test set dependent solution would fail to comply with the standard industrial design flow, as a slight change in the design leads to the re-generation of test patterns, enforcing a costly, if feasible, re-synthesis of the clock network.
Instead, a dynamic and test set independent scan chain partitioning technique that is capable of adapting to the transition distribution of any test pattern is the key to minimizing peak power. A solution that is capable of effecting the chain partitioning on a per pattern basis can be pursued in order to evenly distribute the transitions of any test pattern, adaptively providing the special handling needed for any problematic pattern.
Numerous methodologies that aim at test power reduction in a scan-based environment have been proposed recently. The utilization of externally controlled gates or modified scan cell designs has been shown to reduce test power drastically, albeit at the expense of functional performance degradation due to the additional gate delays introduced on functional paths. Appropriate primary input assignments during the shift cycles help reduce transition propagation from the scan chain to the circuit under test; however, the effectiveness of such techniques is limited as circuits are typically controlled by scan chains rather than primary inputs. Test vector ordering and scan-latch clustering/ordering techniques, modification of test cube compaction and test generation and don't care bit specification procedures constitute a set of alternative techniques for reducing scan power dissipation. However, all of the previous techniques extract test power reductions at the expense of performance degradation, possible layout constraint violations, or prolonged test application time. Furthermore, none of these techniques alleviate the power dissipation problem in the clock network.
A number of scan chain modification techniques for test power reduction have been proposed. These techniques essentially rely on scan chain modifications, which are effected based on the analysis of a test set, in order to transform the test vectors and responses into new stimuli and response vectors with fewer transitions. While significant test power reductions are thus attained, these techniques are test set dependent, and are thus more suitable for application in the core-based SOC domain. Furthermore, clock power dissipation is not reduced by these techniques.
Various other techniques have also been proposed to reduce peak power. The peak power minimization problem is attacked by classifying clock cycles in which peak power violation occurs; bit-stripping and, subsequently, re-specifying the don't care bits are performed in order to reduce the transitions below a given threshold in the problematic cycles. The necessity to manipulate the test patterns is the major drawback in these techniques.
In fact, a closer look into the IR-drop issue and the consequent peak power violations are provided in a test pattern scrubbing technique and various don't care bit specification techniques. However, in these techniques power dissipation in the clock network is not alleviated, because with the shift clock spreading technique, instantaneous power will only be reduced by an offset between the rising edges of the shift clock. In other words, the shift clock that feeds a scan cell ripples through other scan cells prior to reaching this scan cell. To attain both clock power and logic power reduction, however, the scan cell design has to be modified. Furthermore, the shift frequency may have to be reduced in order to account for the rippling of the shift clock through the entire scan chain. Thus, deeper scan chains limit the applicability of this approach.
Scan chain partitioning techniques have also been proposed for test power reduction, wherein the scan chain is decomposed into several partitions so as to have only one of the partitions active at a time during shift mode, during capture mode, or during both shift and capture modes reducing scan chain toggling. The main advantage of these techniques is the fact that they are test set independent and that they can reduce power dissipation in the clock tree also. All these techniques constitute static scan chain partitioning, wherein a single scan chain partitioning is pursued for all the test patterns. While these scan chain segmentation techniques provide reasonable average test power reductions, their effectiveness in reducing peak power may be limited depending on the distribution of transitions for a particular test pattern, which dictates the peak power within the statically constructed partitions.
Thus, a circuit and method providing dynamic scan chain partitioning solving the aforementioned problems are desired.